1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as the flash memory or mask ROM and a method of fabrication thereof.
2. Description of the Related Art
The electrically erasable and programmable read-only memory (EEPROM) has the property that data can be electrically written into or erased from a memory cell. This memory is nonvolatile in that data are not erased even when powered off. The flash-type EEPROM (flash memory), in which data are erased by all bits on block or by a unit of one block, can be configured of a single memory transistor for each memory cell unlike the ordinary EEPROM requiring a memory transistor and a selection transistor for each memory cell. The flash memory, therefore, has the advantage that high integration is possible to the same extent as the EPROM (erasable and programmable read-only memory) of ultraviolet erasing type.
In the EEPROM including the flash memory, the effective length of the channel region (effective channel length) defined by the relative positions of the source diffusion layer and the drain diffusion layer of the memory cell transistor has a considerable effect on the memory cell characteristics including the threshold voltage or drain current in data read operation or the write characteristic in data write operation, for example. As a result, large variations of the effective channel length among memory cells would cause correspondingly great variations in the memory cell characteristics, thereby considerably reducing the reliability of the device or the ratio of good articles.
The source diffusion layer and the drain diffusion layer are formed by ion-implanting impurities into a substrate by self-alignment using a stacked gate structure including a control gate and a floating gate as a mask. The effective channel length, therefore, is determined by two factors including the processing accuracy of the floating gate and the control gate and the lateral expansion (lateral diffusion length) of the source diffusion layer and the drain diffusion layer due to the heat treatment after ion implantation.
In the case where the memory size is reduced in order to increase the memory capacity per unit surface area, the accuracy of the effective channel length is largely dependent on the processing accuracy of the floating gate and the control gate rather than on the lateral diffusion length of impurities. The minimum resolution in exposure of the photoresist, etc., however, makes it difficult to form a minute floating gate or the like with high accuracy. Consequently, the effective channel length is considerably varied among memory cells.
In view of this, a memory cell transistor of DSA (diffusion self-alignment) type is proposed for the nonvolatile semiconductor memory device (for example, JP-A-54-156483). In the DSA-type memory cell transistor, the effective channel length is independent of the processing dimensions or accuracy of the floating gate and the control gate but dependent on the difference between the lateral diffusion lengths of P-type and N-type impurities, and therefore the effective channel length is not varied among memory cells.
In the nonvolatile semiconductor memory device described in the above-described patent publication, however, the channel region providing a P-type impurities diffusion layer is sandwiched in a floating state between an N-type substrate and an N-type drain diffusion layer, and therefore the potential of the channel region cannot be controlled. For this reason, both the read or rewrite operations cause a punch-through, with the result that the threshold voltage is varied among memory cells and stable operation becomes difficult.